Nov 23, 2025

Project Gabriel: AI-Accelerated Formally Verified FPGA Security for Critical Infrastructure

Caleb Parikh

Project Gabriel demonstrates how AI can accelerate the development of formally verified FPGA security systems for critical infrastructure protection. We built an FPGA-based hardware authentication gatekeeper that controls access to microcontroller programming using challenge-response cryptography, with all logic formally verified using SymbiYosys. Our three-stage approach validated that AI (Claude Code) can successfully write Verilog code that passes formal verification, that direct hardware feedback loops enable rapid iterative development, and that adversarial AI testing (red team vs blue team) uncovers specification gaps missed by single-agent development. This work addresses AI safety by demonstrating how AI can make formal verification orders of magnitude cheaper and faster, enabling scalable protection of critical infrastructure and establishing foundations for verifiable compute governance systems essential for international AI agreements.

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Cite this work

@misc {

title={

(HckPrj) Project Gabriel: AI-Accelerated Formally Verified FPGA Security for Critical Infrastructure

},

author={

Caleb Parikh

},

date={

11/23/25

},

organization={Apart Research},

note={Research submission to the research sprint hosted by Apart.},

howpublished={https://apartresearch.com}

}

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This work was done during one weekend by research workshop participants and does not represent the work of Apart Research.
This work was done during one weekend by research workshop participants and does not represent the work of Apart Research.