Feb 2, 2026
Prototyping an Embedded Off-Switch for AI Compute
James Petrie
🏆 5th Place Winner
This project prototypes an embedded off-switch for AI accelerators. The security block requires periodic cryptographic authorization to operate: the chip generates a nonce, an external authority signs it, and the chip verifies the signature before granting time-limited permission. Without valid authorization, outputs are gated to zero. The design was implemented in HardCaml and validated in simulation.
Very interesting stuff. I'd be interested in an analysis of how easy/hard it is for adversaries to tamper with this approach, as well as the extent to which it relies on TEE being robust. The main arguments against off-switches are that they can be manipulated/exploited; would be interesting to think through what information parties would need to be able to truly trust that off-switches were not going to backfire on them.
Would be interested in seeing a discussion of why this project is likely to be implemented / under what conditions it would be/barriers to implementation. I'd like to see an argument about why this is tractable.
Cite this work
@misc {
title={
(HckPrj) Prototyping an Embedded Off-Switch for AI Compute
},
author={
James Petrie
},
date={
2/2/26
},
organization={Apart Research},
note={Research submission to the research sprint hosted by Apart.},
howpublished={https://apartresearch.com}
}


