Prototyping an Embedded Off-Switch for AI Compute
James Petrie
Submitted to The Technical AI Governance Challenge. Sprint projects are early-stage work by participants, not Apart Research publications.
This project prototypes an embedded off-switch for AI accelerators. The security block requires periodic cryptographic authorization to operate: the chip generates a nonce, an external authority signs it, and the chip verifies the signature before granting time-limited permission. Without valid authorization, outputs are gated to zero. The design was implemented in HardCaml and validated in simulation.
Reviews
Would be interested in seeing a discussion of why this project is likely to be implemented / under what conditions it would be/barriers to implementation. I'd like to see an argument about why this is tractable.
Very interesting stuff. I'd be interested in an analysis of how easy/hard it is for adversaries to tamper with this approach, as well as the extent to which it relies on TEE being robust. The main arguments against off-switches are that they can be manipulated/exploited; would be interesting to think through what information parties would need to be able to truly trust that off-switches were not going to backfire on them.
Cite this project
@misc{petrie2026prototyping,
title = {{Prototyping an Embedded Off-Switch for AI Compute}},
author = {James Petrie},
year = {2026},
month = feb,
note = {Submitted to The Technical AI Governance Challenge, an Apart Research Sprint},
howpublished = {\url{https://apartresearch.com/sprints/projects/prototyping-an-embedded-offswitch-for-ai-compute-65pz}},
url = {https://apartresearch.com/sprints/projects/prototyping-an-embedded-offswitch-for-ai-compute-65pz}
}More from The Technical AI Governance Challenge
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